1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit adapted to high speed operation.
2. Description of the Related Art
In these years, the operation speed and the integration density of the integrated circuit have been significantly improved, along with the miniaturization of the semiconductor elements. Particularly, BiCMOS LSI which employs the combination of CMOSFETs and bipolar transistors and enabling high speed operation and low power dissipation, is being developed.
With respect to the memory LSI, however, the fastest memory LSI is the bipolar memory LSI employing the emitter-coupled logic (ECL) circuits. This LSI dissipates a relatively large power and hence is limited in the integration density at most at 64 kbits. With respect to the memory LSI employing CMOSs, LSIs, each including 1 Mbits memory have already been made. The operation speed of these CMOS circuits, however, is slow, being 1/2 to 1/5 of that of the ECL circuits. Therefore, bipolar memories employing the ECL circuits are mainly used in the field of LSI which is required to operate at a high speed. In the memory LSI, the integration density and the operation speed are in a trade-off relationship with the restriction of power dissipation, and the LSI of high integration density can not fully realize high speed performance. LSIs of low power dissipation and of high speed operation have been strongly desired. Under these circumstances, BiCMOS memory LSIs have been attracting attention as memory LSIs of high integration density and high operation speed.
This trend is ascribed to the recent tendency of high speed and high function of electronics instruments.
Miniaturization of semiconductor elements has been advanced to respond this requirement. Fine pattern processings, however, need corresponding facilities and equipments. It is, hence, not easy to rapidly develop the fine pattern processings. Thus, attempts have been performed to enhance the high speed operation by the expedients in the circuit design. For example, high speed memory circuits utilizing pipeline systems are proposed and fabricated as described in JP-B-62-44352 specification and "Interface" August, 1987 issue, page 212 (introducing Brooktree Bt401-404 type bipolar memory, Fujitsu MBM 10423 LL type 1 kbits bipolar memory). In the pipeline system of the invention described in the above-mentioned JP-B-62-44352, a piepline system is proposed performs reading and writing of information at a shorter time interval than the information read time of the memory circuit (address access time: time from the input of an information read signal to the output of a recorded information from a memory cell, hereinafter referred to as access time), by dividing the operation of the memory circuit along the signal flow and operating the respective circuits independently. Further, in the invention described in the above-mentioned specification, in practice there is a need for disposing latch circuits between adjacent divided circuits, and to keep the independence of the divided circuits by supplying clocks to these latch circuits. Namely, according to this approach, latch circuits and clocks are necessary. As the number of divided circuits increase, it is also required to increase the clock frequency. Further, there is also an increase in the delay time due to the provision of the latch circuits. When a memory LSI having an access time of several nano-seconds is to be arranged into a pipeline system to enhance the high speed operation, the merit of the pipeline system is cancelled by the demerit of the provision of latch circuits. Further, in a circuit arranged in the pipeline system, the read information will be outputted at a short time interval. Then, the output buffer circuit is indispensable for supplying the information at the speed determined according to the external request. The memory of Brooktree has made only the information read system into a pipelined system. The memory of Fujitsu has not fully extracted the high speed operability of the pipeline system since the clock cycle time is longer than the access time.